module led (
    input clk,
    input rst,
    input load,
    input [15:0] in_data,
    output [7:0] seg,
    output [2:0] sel
);

  reg [15:0] data;

  reg [16:0] cnt;

  localparam CNT_MAX = 17'd99_999;

  always @(posedge clk or negedge rst) begin
    if (!rst) begin
      data <= 16'd0;
      cnt  <= 17'd0;
    end else if (load) begin
      data <= in_data;
    end else if (cnt == CNT_MAX) begin
      cnt  <= 17'd0;
      data <= data + 1'b1;
    end else begin
      cnt <= cnt + 1'b1;
    end
  end

  display u_display (
      .clk (clk),
      .rst (rst),
      .data(data),
      .seg (seg),
      .sel (sel)
  );

endmodule
